mirror of
https://github.com/lloeki/python-dcpu_16.git
synced 2025-12-06 09:54:39 +01:00
WIP working towards 1.5
This commit is contained in:
parent
a714a9d71a
commit
13adbbf68c
2 changed files with 350 additions and 170 deletions
368
dcpu_16.py
368
dcpu_16.py
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@ -5,12 +5,19 @@ Spec: http://0x10c.com/doc/dcpu-16.txt
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See LICENSE for licensing information.
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"""
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# TODO: cycle count management
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# branching opcodes take one cycle longer to perform if the test fails
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# when they skip an if instruction, they will skip an additional instruction
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# TODO: signed functions
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# signed numbers are represented using two's complement
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# TODO: interrupts
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# TODO: hardware
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from __future__ import print_function, division
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# DCPU-16 spec version
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spec = '1.1'
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spec = '1.5'
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# log tool
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@ -100,131 +107,247 @@ def pointerize(f):
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return ptrz
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@opcode(0x0, 0x01)
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@opcode(0x00, 0x01)
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def JSR(c, a):
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"""pushes the address of the next instruction to the stack, then sets PC to a"""
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c.sp -= 1
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c.m[c.sp] = c.pc
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c.pc = a()
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@opcode(0x1)
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def SET(c, a, b):
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"""sets a to b"""
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a.set(b())
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@opcode(0x00, 0x07)
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def HCF(c, a):
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"""use sparingly"""
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pass
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@opcode(0x2)
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def ADD(c, a, b):
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"""sets a to a+b, sets O to 0x0001 if there's an overflow"""
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res = (a() + b())
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@opcode(0x00, 0x08)
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def INT(c, a):
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"""triggers a software interrupt with message a"""
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pass
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@opcode(0x00, 0x09)
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def IAG(c, a):
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"""sets a to IA"""
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pass
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@opcode(0x00, 0x0A)
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def IAS(c, a):
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"""sets IA to a"""
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pass
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@opcode(0x00, 0x0B)
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def IAP(c, a):
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"""if IA is 0, does nothing, otherwise pushes IA to the stack, then sets IA to a"""
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pass
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@opcode(0x00, 0x0C)
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def IAQ(c, a):
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"""if a is nonzero, interrupts will be added to the queue instead of triggered. if a is zero, interrupts will be triggered as nomral again"""
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pass
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@opcode(0x00, 0x10)
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def HWN(c, a):
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"""sets a to number of connected hardware devices"""
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pass
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@opcode(0x00, 0x11)
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def HWQ(c, a):
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"""sets A, B, C,X, Y registers to information about hardware a
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A+(B<<16) is a 32 bit word identifying the hardware id
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C is the hardware version
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X+(Y<<16) is a 32 bit word identifying the manufacturer
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"""
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pass
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@opcode(0x00, 0x12)
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def HWI(c, a):
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"""sends an interrupt to hardware a"""
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pass
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@opcode(0x01)
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def SET(c, b, a):
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"""sets b to a"""
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b.set(a())
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@opcode(0x02)
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def ADD(c, b, a):
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"""sets b to b+a, sets EX to 0x0001 if there's an overflow, 0x0 otherwise"""
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res = (b() + a())
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if res > wmask:
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c.o = 0x0001
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c.ex = 0x0001
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res = res & wmask
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a.set(res)
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b.set(res)
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@opcode(0x3)
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def SUB(c, a, b):
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"""sets a to a-b, sets O to 0xFFFF if there's an underflow"""
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res = (a() - b())
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@opcode(0x03)
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def SUB(c, b, a):
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"""sets b to b-a, sets EX to 0xFFFF if there's an underflow, 0x0 otherwise"""
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res = (b() - a())
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if res & (wmask+1):
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c.o = 0xFFFF
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c.ex = 0xFFFF
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res = res & wmask
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a.set(res)
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b.set(res)
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@opcode(0x4)
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def MUL(c, a, b):
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"""sets a to a*b, sets O to ((a*b)>>16)&0xFFFF"""
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res = (a() * b())
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c.o = ((a() * b()) >> w) & wmask
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@opcode(0x04)
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def MUL(c, b, a):
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"""sets b to b*a, sets EX to ((b*a)>>16)&0xFFFF (treats b, a as unsigned)"""
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res = (b() * a())
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c.ex = ((b() * a()) >> w) & wmask
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res = res & wmask
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a.set(res)
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b.set(res)
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@opcode(0x5)
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def DIV(c, a, b):
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"""sets a to a/b, sets O to ((a<<16)/b)&0xFFFF"""
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res = a() // b()
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c.o = ((a() << w) // b()) & wmask
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a.set(res)
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@opcode(0x05)
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def MLI(c, b, a):
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"""like MUL, but treats b, a as signed"""
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pass
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@opcode(0x6)
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def MOD(c, a, b):
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"""sets a to a%b. if b==0, sets a to 0 instead"""
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if b()==0:
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@opcode(0x06)
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def DIV(c, b, a):
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"""sets b to b/a, sets EX to ((b<<16)/a)&0xFFFF. if a==0, sets b and EX to 0 instead. (treats b, a as unsigned)"""
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res = b() // a()
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c.ex = ((b() << w) // a()) & wmask
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b.set(res)
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@opcode(0x07)
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def DVI(c, b, a):
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"""like DIV, but treats b, a as signed. Rounds towards 0"""
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pass
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@opcode(0x08)
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def MOD(c, b, a):
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"""sets b to b%a. if a==0 sets b to 0 instead"""
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if a()==0:
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res = 0
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else:
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res = a() % b()
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a.set(res)
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res = b() % a()
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b.set(res)
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@opcode(0x7)
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def SHL(c, a, b):
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"""sets a to a<<b. sets O to ((a<<b)>>16)&0xFFFF"""
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res = (a() << b())
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c.o = ((a() << b()) >> w) & wmask
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@opcode(0x09)
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def MDI(c, b, a):
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"""like MOD, but treat b, a as signed. Rounds towards 0"""
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pass
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@opcode(0x0A)
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def AND(c, b, a):
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"""sets b to b&a"""
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res = b() & a()
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b.set(res)
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@opcode(0x0B)
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def BOR(c, b, a):
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"""sets b to b|a"""
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res = b() | a()
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b.set(res)
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@opcode(0x0C)
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def XOR(c, b, a):
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"""sets b to b^a"""
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res = b() ^ a()
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b.set(res)
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@opcode(0x0D)
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def SHR(c, b, a):
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"""sets b to b>>>a. sets EX to ((b<<16)>>a)&0xFFFF (logical shift)"""
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res = (b() >> a())
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c.ex = ((b() << w) >> a()) & wmask
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res = res & wmask
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a.set(res)
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b.set(res)
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@opcode(0x8)
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def SHR(c, a, b):
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"""sets a to a>>b. sets O to ((a>>16)>>b)&0xFFFF"""
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res = (a() >> b())
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c.o = ((a() >> w) >> b()) & wmask
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@opcode(0x0E)
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def ASR(c, b, a):
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"""sets b to b>>a. sets EX to ((b<<16)>>>a)&0xFFFF (arithmetic shift) (treats b as signed)"""
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pass
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@opcode(0x0F)
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def SHL(c, b, a):
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"""sets b to b<<a. sets EX to ((b<<a)>>16)&0xFFFF"""
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res = (b() << a())
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c.ex = ((b() << a()) >> w) & wmask
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res = res & wmask
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a.set(res)
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b.set(res)
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@opcode(0x9)
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def AND(c, a, b):
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"""sets a to a&b"""
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res = a() & b()
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a.set(res)
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@opcode(0xA)
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def BOR(c, a, b):
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"""sets a to a|b"""
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res = a() | b()
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a.set(res)
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@opcode(0xB)
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def XOR(c, a, b):
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"""sets a to a^b"""
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res = a() ^ b()
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a.set(res)
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@opcode(0xC)
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def IFE(c, a, b):
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"""performs next instruction only if a==b"""
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if a() == b():
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@opcode(0x10)
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def IFB(c, b, a):
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"""performs next instruction only if (b&a)!=0"""
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if (b() & a()) != 0:
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c.skip = False
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else:
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c.skip = True
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@opcode(0xD)
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def IFN(c, a, b):
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"""performs next instruction only if a!=b"""
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if a() != b():
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@opcode(0x11)
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def IFC(c, b, a):
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"""performs next instruction only if (b&a)==0"""
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if (b() & a()) == 0:
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c.skip = False
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else:
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c.skip = True
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@opcode(0xE)
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def IFG(c, a, b):
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"""performs next instruction only if a>b"""
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if a() > b():
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@opcode(0x12)
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def IFE(c, b, a):
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"""performs next instruction only if b==a"""
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if b() == a():
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c.skip = False
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else:
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c.skip = True
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@opcode(0xF)
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def IFB(c, a, b):
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"""performs next instruction only if (a&b)!=0"""
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if (a() & b()) != 0:
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@opcode(0x13)
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def IFN(c, b, a):
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"""performs next instruction only if b!=a"""
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if b() != a():
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c.skip = False
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else:
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c.skip = True
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@opcode(0x14)
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def IFG(c, b, a):
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"""performs next instruction only if b>a"""
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if b() > a():
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c.skip = False
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else:
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c.skip = True
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@opcode(0x15)
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def IFA(c, b, a):
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"""performs next instruction only if b>a (signed)"""
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pass
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@opcode(0x16)
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def IFL(c, b, a):
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"""performs next instruction only if b<a"""
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if b() < a():
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c.skip = False
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else:
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c.skip = True
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@opcode(0x17)
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def IFU(c, b, a):
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"""performs next instruction only if b<a (signed)"""
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pass
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@opcode(0x1A)
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def ADX(c, b, a):
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"""sets b to b+a+EX, sets EX to 0x0001 if there is an overflow, 0x0 otherwise"""
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pass
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@opcode(0x1B)
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def SBX(c, b, a):
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"""sets b to b-a+EX, sets EX to 0xFFFF if there is an underflow, 0x0 otherwise"""
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pass
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@opcode(0x1E)
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def STI(c, b, a):
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"""sets b to a, then increases I and J by 1"""
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pass
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@opcode(0x1F)
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def STD(c, b, a):
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"""sets b to a, then decreases I and J by 1"""
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pass
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@valcode(range(0x00, 0x08))
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@pointerize
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def register(c, code):
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"""register"""
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"""register (A, B, C, X, Y, Z, I, J, in that order)"""
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v = "c.r[0x%01X]" % code
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return v
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@ -245,8 +368,16 @@ def next_word_plus_register_value(c, code):
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@valcode(0x18)
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@pointerize
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def push_pop(c):
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"""(PUSH / [--SP]) if in b, or (POP / [SP++]) if in a"""
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pass
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def push(c):
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"""[--SP] / PUSH"""
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c.sp -= 1
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v = "c.m[0x%04X]" % c.sp
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return v
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def pop(c):
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"""POP / [SP++]"""
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"""[SP++] / POP"""
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v = "c.m[0x%04X]" % c.sp
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c.sp += 1
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return v
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@ -254,37 +385,35 @@ def pop(c):
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@valcode(0x19)
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@pointerize
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def peek(c):
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"""PEEK / [SP]"""
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"""[SP] / PEEK"""
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v = "c.m[0x%04X]" % c.sp
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return v
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@valcode(0x1A)
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@pointerize
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def push(c):
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"""PUSH / [--SP]"""
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c.sp -= 1
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v = "c.m[0x%04X]" % c.sp
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return v
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def pick(c):
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"""[SP + next word] / PICK n"""
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pass
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@valcode(0x1B)
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@pointerize
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def stack_pointer(c):
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"""stack pointer"""
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"""SP"""
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v = "c.sp"
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return v
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@valcode(0x1C)
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@pointerize
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def program_counter(c):
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"""program counter"""
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"""PC"""
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v = "c.pc"
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return v
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@valcode(0x1D)
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@pointerize
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def overflow(c):
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"""overflow"""
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v = "c.o"
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def excess(c):
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"""EX"""
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v = "c.ex"
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return v
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@valcode(0x1E)
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@ -306,8 +435,8 @@ def next_word(c):
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@valcode(range(0x20, 0x40))
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@pointerize
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def literal(c, code):
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"""literal value 0x00-0x1F (literal)"""
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v = "0x%04X" % (code - 0x20)
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"""literal value 0xFFFF-0x1E (-1..30) (literal) (only for a)"""
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v = "0x%04X" % ((code - 0x20 - 1) & 0xFFFF)
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return v
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@ -345,7 +474,7 @@ class CPU(object):
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c.r = [0 for _ in xrange(0, 8)]
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c.pc = 0x0000
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c.sp = 0x0000
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c.o = 0x0000
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c.ex = 0x0000
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c.skip = False
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def clear(c):
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@ -362,22 +491,22 @@ class CPU(object):
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j = Register(0x7)
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pc = Register()
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sp = Register()
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o = Register()
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ex = Register()
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def _op(c, word):
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"""dispatch word to op and args"""
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opcode = word & 0xF
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a_code = word >> 4 & 0x3F
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b_code = word >> 10 & 0x3F
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opcode = word & 0x1F
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b_code = word >> 5 & 0x1F
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a_code = word >> 10 & 0x3F
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try:
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op = _opcode_map[opcode]
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try:
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op = op[a_code]
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except TypeError:
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args = (c._pointer(a_code),
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c._pointer(b_code))
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args = (c._pointer(b_code),
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c._pointer(a_code))
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else:
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args = (c._pointer(b_code),)
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args = (c._pointer(a_code),)
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finally:
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if c.debug:
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log(' '.join([op.__name__] + [arg.codestr for arg in args]))
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@ -428,9 +557,9 @@ class CPU(object):
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(["A", "B", "C",
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"X", "Y", "Z",
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"I", "J",
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"PC", "SP", "O",
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"PC", "SP", "EX",
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][i],
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(c.r + [c.pc, c.sp, c.o])[i])
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(c.r + [c.pc, c.sp, c.ex])[i])
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for i in range(11))
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def load_m(c, data=None, io=None):
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@ -446,8 +575,25 @@ class CPU(object):
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spec_demo = [
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0x7c01, 0x0030, 0x7de1, 0x1000, 0x0020, 0x7803, 0x1000, 0xc00d,
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0x7dc1, 0x001a, 0xa861, 0x7c01, 0x2000, 0x2161, 0x2000, 0x8463,
|
||||
0x806d, 0x7dc1, 0x000d, 0x9031, 0x7c10, 0x0018, 0x7dc1, 0x001a,
|
||||
0x9037, 0x61c1, 0x7dc1, 0x001a, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
# TODO: hand-reassembled for 1.5, but still some bugs
|
||||
0x7c01, 0x0030, # SET A, 0x30
|
||||
0x7fc1, 0x1000, 0x0020, # SET [0x1000], 0x20
|
||||
0x7803, 0x1000, # SUB A, [0X1000]
|
||||
0xc012, # 0xc013 # IFE A, 0xF
|
||||
0x7f81, 0x001a, # SET PC, crash
|
||||
0x90c1, # 0xacc1 # SET I, 10
|
||||
0x7c01, 0x2000, # SET A, 0x2000
|
||||
# :loop
|
||||
0x22C1, 0x2000, # SET [I + 0x2000], [A]
|
||||
0x88C3, # SUB I, 1
|
||||
0x84D3, # IFN I, 0
|
||||
0x7f81, 0x000d, # SET PC, loop
|
||||
0x9461, # SET X, 4
|
||||
0x7c20, 0x0018, # JSR testsub
|
||||
0x7f81, 0x001a, # SET PC, crash
|
||||
# :testsub
|
||||
0x946f, # SHL X, 4
|
||||
0x6381, # SET PC, POP
|
||||
# :crash
|
||||
0x7f81, 0x001a, # SET PC, crash
|
||||
]
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue