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50ab21f3e5
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skip feedback
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2012-04-09 11:30:21 +02:00 |
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f3acea29fd
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fix param order to match doc
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2012-04-09 11:27:06 +02:00 |
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54e56b82db
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updated doc and brought back spec demo
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2012-04-08 20:01:41 +02:00 |
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a2c029f9cb
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spec demo program as a test
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2012-04-08 19:58:24 +02:00 |
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32a827b728
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cosmetic
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2012-04-08 19:57:50 +02:00 |
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5fa919e35b
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uniform naming
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2012-04-08 19:57:02 +02:00 |
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3f559dcf32
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naive nib dispatch. should not be so complex.
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2012-04-08 18:26:17 +02:00 |
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060ed1662f
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fixing conditionals
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2012-04-08 18:25:00 +02:00 |
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930a04473c
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JSR implemented
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2012-04-08 18:24:39 +02:00 |
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7f97d50ce0
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guarding against PC/SP overflow
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2012-04-08 18:24:05 +02:00 |
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6d5a40d6ac
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integer division
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2012-04-08 18:21:26 +02:00 |
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0b1f2a84ef
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fix [next word + register] not using reg value
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2012-04-08 18:20:25 +02:00 |
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a2d39a818b
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log only when debug set
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2012-04-08 18:18:50 +02:00 |
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9fcfd9437d
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register accessors by name
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2012-04-08 18:16:50 +02:00 |
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9d60e6c907
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hex output
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2012-04-06 11:30:59 +02:00 |
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be5c3baae4
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fix evaluation order, per spec (a then b)
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2012-04-06 11:30:33 +02:00 |
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e78f4b8af8
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since it's more advanced, using test.py
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2012-04-05 23:48:29 +02:00 |
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ff63a59cac
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almost there, for an initial impl.
ironically test.py ended up way more advanced than dcpu_16.py
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2012-04-05 23:45:16 +02:00 |
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