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45e71c9ff5
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fix spec_demo
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2012-04-29 12:26:08 +02:00 |
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a5823b5dd4
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spec 1.5 reference
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2012-04-29 12:25:29 +02:00 |
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13adbbf68c
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WIP working towards 1.5
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2012-04-27 17:07:05 +02:00 |
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a714a9d71a
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guard against SET PC, [SP++], and SET PC, [--SP]
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2012-04-14 15:41:20 +02:00 |
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d638ebe7ea
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docstring
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2012-04-14 15:39:42 +02:00 |
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d95072ceb4
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doc + cosmetic
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2012-04-09 16:17:30 +02:00 |
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bf055e998e
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Isolate memory from CPU
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2012-04-09 16:16:22 +02:00 |
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7d6205cac9
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all registers wrapped as 16 bits
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2012-04-09 15:58:44 +02:00 |
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9a11985cb6
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simplified register declaration
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2012-04-09 15:40:40 +02:00 |
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4d2d914712
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log outside of valcodes
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2012-04-09 15:32:51 +02:00 |
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39ac76aa4f
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exception isolation
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2012-04-09 15:32:14 +02:00 |
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6f493aab4e
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cosmetic
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2012-04-09 15:13:56 +02:00 |
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605790257f
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refactored opcode dispatching
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2012-04-09 15:13:15 +02:00 |
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037559160f
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a little doc
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2012-04-09 11:48:36 +02:00 |
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2fff97dd64
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run(), and HLT on infinite loop
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2012-04-09 11:47:14 +02:00 |
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50ab21f3e5
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skip feedback
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2012-04-09 11:30:21 +02:00 |
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f3acea29fd
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fix param order to match doc
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2012-04-09 11:27:06 +02:00 |
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6fcac3cf2e
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title changes
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2012-04-08 20:19:55 +02:00 |
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c3e7012f2d
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Updated doc
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2012-04-08 20:16:57 +02:00 |
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54e56b82db
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updated doc and brought back spec demo
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2012-04-08 20:01:41 +02:00 |
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ec4711d2af
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ignore pyc
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2012-04-08 19:58:53 +02:00 |
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726698b4ea
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cosmetic
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2012-04-08 19:58:35 +02:00 |
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a2c029f9cb
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spec demo program as a test
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2012-04-08 19:58:24 +02:00 |
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32a827b728
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cosmetic
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2012-04-08 19:57:50 +02:00 |
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5fa919e35b
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uniform naming
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2012-04-08 19:57:02 +02:00 |
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3f559dcf32
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naive nib dispatch. should not be so complex.
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2012-04-08 18:26:17 +02:00 |
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060ed1662f
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fixing conditionals
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2012-04-08 18:25:00 +02:00 |
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930a04473c
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JSR implemented
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2012-04-08 18:24:39 +02:00 |
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7f97d50ce0
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guarding against PC/SP overflow
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2012-04-08 18:24:05 +02:00 |
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6d5a40d6ac
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integer division
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2012-04-08 18:21:26 +02:00 |
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0b1f2a84ef
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fix [next word + register] not using reg value
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2012-04-08 18:20:25 +02:00 |
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a2d39a818b
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log only when debug set
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2012-04-08 18:18:50 +02:00 |
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9fcfd9437d
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register accessors by name
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2012-04-08 18:16:50 +02:00 |
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5c50feec31
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unit tests
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2012-04-08 18:16:13 +02:00 |
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bec3aea0a1
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fixing links
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2012-04-06 12:46:04 +02:00 |
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93f16365d9
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a few links
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2012-04-06 12:45:12 +02:00 |
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d399ea3c5f
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features section
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2012-04-06 12:31:35 +02:00 |
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1068870103
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status info
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2012-04-06 12:18:12 +02:00 |
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cca2f8453b
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be precise
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2012-04-06 12:14:47 +02:00 |
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a9bfc51938
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REPL example, not just code
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2012-04-06 12:12:44 +02:00 |
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6bb632cf85
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cosmetic fix
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2012-04-06 12:07:55 +02:00 |
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462a2993ea
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cosmetic stuff
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2012-04-06 12:07:00 +02:00 |
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98c8e4a4bb
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markdown, duh.
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2012-04-06 12:05:39 +02:00 |
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7daaee059b
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README
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2012-04-06 12:04:56 +02:00 |
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0c8e0f7acc
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3-Clause BSD license
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2012-04-06 11:50:29 +02:00 |
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9d60e6c907
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hex output
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2012-04-06 11:30:59 +02:00 |
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be5c3baae4
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fix evaluation order, per spec (a then b)
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2012-04-06 11:30:33 +02:00 |
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e78f4b8af8
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since it's more advanced, using test.py
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2012-04-05 23:48:29 +02:00 |
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ff63a59cac
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almost there, for an initial impl.
ironically test.py ended up way more advanced than dcpu_16.py
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2012-04-05 23:45:16 +02:00 |
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