Commit graph

28 commits

Author SHA1 Message Date
726698b4ea cosmetic 2012-04-08 19:58:35 +02:00
a2c029f9cb spec demo program as a test 2012-04-08 19:58:24 +02:00
32a827b728 cosmetic 2012-04-08 19:57:50 +02:00
5fa919e35b uniform naming 2012-04-08 19:57:02 +02:00
3f559dcf32 naive nib dispatch. should not be so complex. 2012-04-08 18:26:17 +02:00
060ed1662f fixing conditionals 2012-04-08 18:25:00 +02:00
930a04473c JSR implemented 2012-04-08 18:24:39 +02:00
7f97d50ce0 guarding against PC/SP overflow 2012-04-08 18:24:05 +02:00
6d5a40d6ac integer division 2012-04-08 18:21:26 +02:00
0b1f2a84ef fix [next word + register] not using reg value 2012-04-08 18:20:25 +02:00
a2d39a818b log only when debug set 2012-04-08 18:18:50 +02:00
9fcfd9437d register accessors by name 2012-04-08 18:16:50 +02:00
5c50feec31 unit tests 2012-04-08 18:16:13 +02:00
bec3aea0a1 fixing links 2012-04-06 12:46:04 +02:00
93f16365d9 a few links 2012-04-06 12:45:12 +02:00
d399ea3c5f features section 2012-04-06 12:31:35 +02:00
1068870103 status info 2012-04-06 12:18:12 +02:00
cca2f8453b be precise 2012-04-06 12:14:47 +02:00
a9bfc51938 REPL example, not just code 2012-04-06 12:12:44 +02:00
6bb632cf85 cosmetic fix 2012-04-06 12:07:55 +02:00
462a2993ea cosmetic stuff 2012-04-06 12:07:00 +02:00
98c8e4a4bb markdown, duh. 2012-04-06 12:05:39 +02:00
7daaee059b README 2012-04-06 12:04:56 +02:00
0c8e0f7acc 3-Clause BSD license 2012-04-06 11:50:29 +02:00
9d60e6c907 hex output 2012-04-06 11:30:59 +02:00
be5c3baae4 fix evaluation order, per spec (a then b) 2012-04-06 11:30:33 +02:00
e78f4b8af8 since it's more advanced, using test.py 2012-04-05 23:48:29 +02:00
ff63a59cac almost there, for an initial impl.
ironically test.py ended up way more advanced than dcpu_16.py
2012-04-05 23:45:16 +02:00